Vertical nanowire transistors with low leakage current
نویسندگان
چکیده
منابع مشابه
Towards Sub-10 nm Diameter III-V Vertical Nanowire Transistors
Towards the demonstration of sub-10 nm III-V vertical fin and nanowire MOSFETs, a novel alcohol-based digital-etch technology has been developed. The new technique minimizes the mechanical forces exerted on vertical nanowire structures. A consistent 1 nm/cycle etching rate on both InGaAs and InGaSb-based heterostructures has been obtained. This is the first demonstration of digital etch on anti...
متن کاملCore-shell homojunction silicon vertical nanowire tunneling field-effect transistors
We propose three-terminal core-shell (CS) silicon vertical nanowire tunneling field-effect transistors (TFETs), which can be fabricated by conventional CMOS technology. CS TFETs show lower subthreshold swing (SS) and higher on-state current than conventional TFETs through their high surface-to-volume ratio, which increases carrier-tunneling region with no additional device area. The on-state cu...
متن کاملVertical nanowire array-based field effect transistors for ultimate scaling.
Nanowire-based field-effect transistors are among the most promising means of overcoming the limits of today's planar silicon electronic devices, in part because of their suitability for gate-all-around architectures, which provide perfect electrostatic control and facilitate further reductions in "ultimate" transistor size while maintaining low leakage currents. However, an architecture combin...
متن کاملLow-leakage SRAM Design with Dual Vt Transistors
This paper presents a method based on dual threshold voltage assignment to reduce the leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that the read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. The key idea is thus to realize and depl...
متن کاملLeakage Current Calibration Procedures of Amorphous Silicon Thin-Film Transistors
Figure 1. (a) Trap occupancy of a trapping level under non-equilibrium conditions (b) probability of occupation (c) conceptual diagram of DOS, probability of occupation, and ionized densities in the a-Si TFTs. Figure 2. Examples of ATLAS simulation results with DEFECT and SAVE TRAP.FILE statements. Introduction Amorphous silicon Thin-Film Transistors (a-Si TFTs) are widely used as the switching...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Applied Physics Letters
سال: 2004
ISSN: 0003-6951,1077-3118
DOI: 10.1063/1.1784037